1. Field of the Invention
This invention relates to a liquid crystal display. More particularly, it relates to a liquid crystal display and to a method of fabricating that display.
2. Description of the Related Art
Generally, an active matrix liquid crystal display (LCD) uses thin film transistors (TFT's) as switching devices. Such displays are capable of producing high quality moving images. Since LCD's can be made relatively small, they have become widely used as displays for personal computers, notebook computer, office automation equipment such as copiers, and portable devices such as cellular phones.
Fabricating an active matrix LCD includes substrate cleaning, substrate patterning, alignment film formation, substrate adhesion, liquid crystal injection, packaging, and testing.
In substrate cleaning, a cleaner removes foreign substances from an upper substrate and from a lower substrate, both before and after patterning.
Substrate patterning involves providing an upper substrate and a lower substrate. The upper substrate has color filters, a common electrode and a black matrix. The lower substrate includes signal conductors, such as data lines and gate lines, and a thin film transistor (TFT) at the intersections of the data lines and the gate lines. The lower substrate also has pixel electrodes at pixel areas between the data lines and the gate lines.
Substrate adhesion and liquid crystal injection involves coating an alignment film on the lower substrate, rubbing the alignment film to provide for liquid crystal alignment, and adhering the upper substrate to the lower substrate using a sealant. A liquid crystal is then injected through an injection hole, which is then sealed. The sealant assists defining a space for the liquid crystal.
A dummy seal has been used to assist substrate adhesion and to provide for a uniform cell gap. This is described in more detail with the assistance of FIG. 1 and FIG. 2. FIG. 1 illustrates a conventional LCD device having a lower substrate 1, an upper substrate 2, and a seal 3 on the lower substrate. Dummy seals 8A to 8D are also provided.
The main seal 3 defines a space for receiving a liquid crystal and for producing a picture display area 5. One side of the main seal includes a liquid crystal injection opening 4. The liquid crystal is injected through the liquid crystal injection opening 4. The dummy seals 8A to 8D are arranged outside the main seal 3. Those dummy seals have the same thickness as the main seal 3.
At the picture display area 5 the lower substrate 1 has data lines that receive video signals, and gate lines that receive scanning signals. The data lines and the gate lines perpendicularly intersect. At each intersection is a TFT that is used for switching a liquid crystal cell. A pixel electrode in the liquid crystal cell connects to the TFT. Further, the lower substrate 1 also includes data pads 6 that connect to the data lines, and gate pads 7 that connect to the gate lines. Those pads are formed outside of the main seal 3. The gate pads 7 apply scanning signals, in the form of gate pulses from a gate driving integrated circuit (IC), to the gate lines via gate links 10. The data pads 6 apply video signals from a data driving IC to the data lines via data links 9. The data pads 6 and the gate pads 7 typically connect to the data driving IC and to the gate driving IC, respectively, by a tape automated bonding (TAB) system that employs a tape carrier package (TCP), or by a chip on glass (COG) system having a circuit that is directly mounted on the substrate.
The upper substrate 2 includes a black matrix, color filters, and a common electrode (not shown). The black matrix is formed at interface areas between the liquid crystal cells so as to reduce optical interference between those cells. The color filters selectively transmit light having specific color bands so as to produce red (R), green (G), and blue (B) colors.
In the conventional LCD panel shown in FIG. 1 although the dummy seals 8A to 8D are provided, the height of the layers formed on the lower substrate 1 vary. Referring now to FIG. 2, this variance is a result of differences in the number and the thicknesses of the layers under the main seal 3 and under the dummy seals 8A to 8D. This produces seal steps.
Along lines A–A′, F–F′, G–G′ and H–H′ in FIG. 1, the dummy seals 8A to 8D are formed only on the lower substrate 1. Those seals have a thickness of approximately 6000 Å.
At the gate link area along line B–B′ of FIG. 1, the lower substrate 1 has stacked layers each comprised of a gate metal layer 20, a gate-insulating layer 21, an active layer 22 and a passivation layer 23. The stacked layers have a thickness of approximately 10300 Å. Furthermore, an unstacked area exists between the stacked-layers. The main seal 3 is coated over the structures in the gate link area at line B–B′. The result is that the main seal 3 has an uneven top surface, which is higher than the top surface of the dummy seals along lines A–A′, F–F′, G–G′ and H–H′ of FIG. 1.
At the data link area 9 along line C–C′ of FIG. 1, on the lower substrate 1 are stacked layers, each comprised of a gate-insulating layer 21, an active layer 22, a source/drain metal layer 24 and a passivation layer 23. Those stacked layers have a thickness of approximately 9500 Å. Furthermore, an unstacked area exists between those stacked-layers. The main seal 3 is coated over the structures in the data link area at lines C–C′. The result is that the main seal 3 has an uneven top surface.
At the liquid crystal injection hole area along line D–D′ of FIG. 1, on the lower substrate 1 are a gate metal layer 20, a gate-insulating layer 21, a source/drain metal layer 24 and a passivation layer 23. Those layers have a thickness of approximately 10000 Å. The main seal 3 is coated over the structures in the liquid crystal injection hole area at lines D–D′.
At the lower area of the main seal 3 along line E–E′ of FIG. 1, on the lower substrate 1 are stacked layers, each comprised of a gate metal layer 20, a gate-insulating layer 21, a source/drain metal layer 24, and a passivation layer 23. Those stacked layers have a thickness of approximately 10000 Å. The main seal 3 is coated over the structures in the liquid crystal injection hole area at lines E–E′.
Accordingly, in the conventional LCD panel illustrated in FIG. 1 and FIG. 2, the stacked-layer thicknesses of the dummy seals 8A to 8D and the main seal 3 vary. Thus, a uniform force is not applied to the substrate after adhesion of the upper substrate 2 to the lower substrate 1. As a result, the spacing between the upper and lower substrates 2 and 1 is non-uniform. This can cause display quality deterioration.
Therefore, a liquid crystal display device, and a method of fabricating that liquid crystal display device, having a uniform cell gap would be beneficial.